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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>CASP, CASPA, CASPAL, CASPL -- A64</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CASP, CASPA, CASPAL, CASPL</h2>
      <p class="aml">Compare and Swap Pair of words or doublewords in memory reads a pair of 32-bit words or 64-bit doublewords from memory, and compares them against the values held in the first pair of registers. If the comparison is equal, the values in the second pair of registers are written to memory. If the writes are performed, the reads and writes occur atomically such that no other modification of the memory location can take place between the reads and writes.</p>
      <ul>
        <li><span class="asm-code">CASPA</span> and <span class="asm-code">CASPAL</span> load from memory with acquire semantics.</li>
        <li><span class="asm-code">CASPL</span> and <span class="asm-code">CASPAL</span> store to memory with release semantics.</li>
        <li><span class="asm-code">CASP</span> has neither acquire nor release semantics.</li>
      </ul>
      <p class="aml">For more information about memory ordering semantics, see <a class="armarm-xref" title="Reference to Armv8 ARM section">Load-Acquire, Store-Release</a>.</p>
      <p class="aml">For information about memory accesses, see <a class="armarm-xref" title="Reference to Armv8 ARM section">Load/Store addressing modes</a>.</p>
      <p class="aml">The architecture permits that the data read clears any exclusive monitors associated with that location, even if the compare subsequently fails.</p>
      <p class="aml">If the instruction generates a synchronous Data Abort, the registers which are compared and loaded, that is &lt;Ws&gt; and &lt;W(s+1)&gt;, or &lt;Xs&gt; and &lt;X(s+1)&gt;, are restored to the values held in the registers before the instruction was executed.</p>
    
    <h3 class="classheading"><a id="iclass_base_register"/>No offset<span style="font-size:smaller;"><br/>(FEAT_LSE)
          </span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">0</td><td class="lr">sz</td><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">L</td><td class="lr">1</td><td colspan="5" class="lr">Rs</td><td class="lr">o0</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td class="r">1</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rt</td></tr><tr class="secondrow"><td/><td/><td colspan="6"/><td/><td/><td/><td colspan="5"/><td/><td colspan="5" class="droppedname">Rt2</td><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">32-bit CASP<span class="bitdiff"> (sz == 0 &amp;&amp; L == 0 &amp;&amp; o0 == 0)</span></h4><a id="CASP_CP32_comswappr"/><p class="asm-code">CASP  <a href="#sa_ws" title="First 32-bit general-purpose register to be compared and loaded (field &quot;Rs&quot;)">&lt;Ws&gt;</a>, <a href="#sa_w_s_plus_1" title="Second 32-bit general-purpose register to be compared and loaded">&lt;W(s+1)&gt;</a>, <a href="#sa_wt" title="First 32-bit general-purpose register to be conditionally stored (field &quot;Rt&quot;)">&lt;Wt&gt;</a>, <a href="#sa_w_t_plus_1" title="Second 32-bit general-purpose register to be conditionally stored">&lt;W(t+1)&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>{,#0}]</p></div><div class="encoding"><h4 class="encoding">32-bit CASPA<span class="bitdiff"> (sz == 0 &amp;&amp; L == 1 &amp;&amp; o0 == 0)</span></h4><a id="CASPA_CP32_comswappr"/><p class="asm-code">CASPA  <a href="#sa_ws" title="First 32-bit general-purpose register to be compared and loaded (field &quot;Rs&quot;)">&lt;Ws&gt;</a>, <a href="#sa_w_s_plus_1" title="Second 32-bit general-purpose register to be compared and loaded">&lt;W(s+1)&gt;</a>, <a href="#sa_wt" title="First 32-bit general-purpose register to be conditionally stored (field &quot;Rt&quot;)">&lt;Wt&gt;</a>, <a href="#sa_w_t_plus_1" title="Second 32-bit general-purpose register to be conditionally stored">&lt;W(t+1)&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>{,#0}]</p></div><div class="encoding"><h4 class="encoding">32-bit CASPAL<span class="bitdiff"> (sz == 0 &amp;&amp; L == 1 &amp;&amp; o0 == 1)</span></h4><a id="CASPAL_CP32_comswappr"/><p class="asm-code">CASPAL  <a href="#sa_ws" title="First 32-bit general-purpose register to be compared and loaded (field &quot;Rs&quot;)">&lt;Ws&gt;</a>, <a href="#sa_w_s_plus_1" title="Second 32-bit general-purpose register to be compared and loaded">&lt;W(s+1)&gt;</a>, <a href="#sa_wt" title="First 32-bit general-purpose register to be conditionally stored (field &quot;Rt&quot;)">&lt;Wt&gt;</a>, <a href="#sa_w_t_plus_1" title="Second 32-bit general-purpose register to be conditionally stored">&lt;W(t+1)&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>{,#0}]</p></div><div class="encoding"><h4 class="encoding">32-bit CASPL<span class="bitdiff"> (sz == 0 &amp;&amp; L == 0 &amp;&amp; o0 == 1)</span></h4><a id="CASPL_CP32_comswappr"/><p class="asm-code">CASPL  <a href="#sa_ws" title="First 32-bit general-purpose register to be compared and loaded (field &quot;Rs&quot;)">&lt;Ws&gt;</a>, <a href="#sa_w_s_plus_1" title="Second 32-bit general-purpose register to be compared and loaded">&lt;W(s+1)&gt;</a>, <a href="#sa_wt" title="First 32-bit general-purpose register to be conditionally stored (field &quot;Rt&quot;)">&lt;Wt&gt;</a>, <a href="#sa_w_t_plus_1" title="Second 32-bit general-purpose register to be conditionally stored">&lt;W(t+1)&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>{,#0}]</p></div><div class="encoding"><h4 class="encoding">64-bit CASP<span class="bitdiff"> (sz == 1 &amp;&amp; L == 0 &amp;&amp; o0 == 0)</span></h4><a id="CASP_CP64_comswappr"/><p class="asm-code">CASP  <a href="#sa_xs" title="First 64-bit general-purpose register to be compared and loaded (field &quot;Rs&quot;)">&lt;Xs&gt;</a>, <a href="#sa_x_s_plus_1" title="Second 64-bit general-purpose register to be compared and loaded">&lt;X(s+1)&gt;</a>, <a href="#sa_xt" title="First 64-bit general-purpose register to be conditionally stored (field &quot;Rt&quot;)">&lt;Xt&gt;</a>, <a href="#sa_x_t_plus_1" title="Second 64-bit general-purpose register to be conditionally stored">&lt;X(t+1)&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>{,#0}]</p></div><div class="encoding"><h4 class="encoding">64-bit CASPA<span class="bitdiff"> (sz == 1 &amp;&amp; L == 1 &amp;&amp; o0 == 0)</span></h4><a id="CASPA_CP64_comswappr"/><p class="asm-code">CASPA  <a href="#sa_xs" title="First 64-bit general-purpose register to be compared and loaded (field &quot;Rs&quot;)">&lt;Xs&gt;</a>, <a href="#sa_x_s_plus_1" title="Second 64-bit general-purpose register to be compared and loaded">&lt;X(s+1)&gt;</a>, <a href="#sa_xt" title="First 64-bit general-purpose register to be conditionally stored (field &quot;Rt&quot;)">&lt;Xt&gt;</a>, <a href="#sa_x_t_plus_1" title="Second 64-bit general-purpose register to be conditionally stored">&lt;X(t+1)&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>{,#0}]</p></div><div class="encoding"><h4 class="encoding">64-bit CASPAL<span class="bitdiff"> (sz == 1 &amp;&amp; L == 1 &amp;&amp; o0 == 1)</span></h4><a id="CASPAL_CP64_comswappr"/><p class="asm-code">CASPAL  <a href="#sa_xs" title="First 64-bit general-purpose register to be compared and loaded (field &quot;Rs&quot;)">&lt;Xs&gt;</a>, <a href="#sa_x_s_plus_1" title="Second 64-bit general-purpose register to be compared and loaded">&lt;X(s+1)&gt;</a>, <a href="#sa_xt" title="First 64-bit general-purpose register to be conditionally stored (field &quot;Rt&quot;)">&lt;Xt&gt;</a>, <a href="#sa_x_t_plus_1" title="Second 64-bit general-purpose register to be conditionally stored">&lt;X(t+1)&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>{,#0}]</p></div><div class="encoding"><h4 class="encoding">64-bit CASPL<span class="bitdiff"> (sz == 1 &amp;&amp; L == 0 &amp;&amp; o0 == 1)</span></h4><a id="CASPL_CP64_comswappr"/><p class="asm-code">CASPL  <a href="#sa_xs" title="First 64-bit general-purpose register to be compared and loaded (field &quot;Rs&quot;)">&lt;Xs&gt;</a>, <a href="#sa_x_s_plus_1" title="Second 64-bit general-purpose register to be compared and loaded">&lt;X(s+1)&gt;</a>, <a href="#sa_xt" title="First 64-bit general-purpose register to be conditionally stored (field &quot;Rt&quot;)">&lt;Xt&gt;</a>, <a href="#sa_x_t_plus_1" title="Second 64-bit general-purpose register to be conditionally stored">&lt;X(t+1)&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>{,#0}]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-shared.HaveAtomicExt.0" title="function: boolean HaveAtomicExt()">HaveAtomicExt</a>() then UNDEFINED;
if Rs&lt;0&gt; == '1' then UNDEFINED;
if Rt&lt;0&gt; == '1' then UNDEFINED;

integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer t = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rt);
integer s = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rs);

integer datasize = 32 &lt;&lt; <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(sz);
boolean acquire = L == '1';
boolean release = o0 == '1';
boolean tagchecked = n != 31;</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Ws&gt;</td><td><a id="sa_ws"/>
        
          <p class="aml">Is the 32-bit name of the first general-purpose register to be compared and loaded, encoded in the "Rs" field. &lt;Ws&gt; must be an even-numbered register.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;W(s+1)&gt;</td><td><a id="sa_w_s_plus_1"/>
        
          <p class="aml">Is the 32-bit name of the second general-purpose register to be compared and loaded.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Wt&gt;</td><td><a id="sa_wt"/>
        
          <p class="aml">Is the 32-bit name of the first general-purpose register to be conditionally stored, encoded in the "Rt" field. &lt;Wt&gt; must be an even-numbered register.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;W(t+1)&gt;</td><td><a id="sa_w_t_plus_1"/>
        
          <p class="aml">Is the 32-bit name of the second general-purpose register to be conditionally stored.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xs&gt;</td><td><a id="sa_xs"/>
        
          <p class="aml">Is the 64-bit name of the first general-purpose register to be compared and loaded, encoded in the "Rs" field. &lt;Xs&gt; must be an even-numbered register.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;X(s+1)&gt;</td><td><a id="sa_x_s_plus_1"/>
        
          <p class="aml">Is the 64-bit name of the second general-purpose register to be compared and loaded.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xt&gt;</td><td><a id="sa_xt"/>
        
          <p class="aml">Is the 64-bit name of the first general-purpose register to be conditionally stored, encoded in the "Rt" field. &lt;Xt&gt; must be an even-numbered register.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;X(t+1)&gt;</td><td><a id="sa_x_t_plus_1"/>
        
          <p class="aml">Is the 64-bit name of the second general-purpose register to be conditionally stored.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xn|SP&gt;</td><td><a id="sa_xn_sp"/>
        
          <p class="aml">Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</p>
        
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode">bits(64) address;
bits(2*datasize) comparevalue;
bits(2*datasize) newvalue;
bits(2*datasize) data;

bits(datasize) s1 = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[s, datasize];
bits(datasize) s2 = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[s+1, datasize];
bits(datasize) t1 = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[t, datasize];
bits(datasize) t2 = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[t+1, datasize];

<a href="shared_pseudocode.html#AccessDescriptor" title="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a href="shared_pseudocode.html#impl-shared.CreateAccDescAtomicOp.4" title="function: AccessDescriptor CreateAccDescAtomicOp(MemAtomicOp modop, boolean acquire, boolean release, boolean tagchecked)">CreateAccDescAtomicOp</a>(<a href="shared_pseudocode.html#MemAtomicOp_CAS" title="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_CAS</a>, acquire, release, tagchecked);

comparevalue = if <a href="shared_pseudocode.html#impl-shared.BigEndian.1" title="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then s1:s2 else s2:s1;
newvalue = if <a href="shared_pseudocode.html#impl-shared.BigEndian.1" title="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then t1:t2 else t2:t1;
if n == 31 then
    <a href="shared_pseudocode.html#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
    address = <a href="shared_pseudocode.html#impl-aarch64.SP.read.0" title="accessor: bits(64) SP[]">SP</a>[];
else
    address = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];

data = <a href="shared_pseudocode.html#impl-aarch64.MemAtomic.4" title="function: bits(size) MemAtomic(bits(64) address, bits(size) cmpoperand, bits(size) operand, AccessDescriptor accdesc_in)">MemAtomic</a>(address, comparevalue, newvalue, accdesc);

if <a href="shared_pseudocode.html#impl-shared.BigEndian.1" title="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then
    <a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[s, datasize] = data&lt;2*datasize-1:datasize&gt;;
    <a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[s+1, datasize] = data&lt;datasize-1:0&gt;;
else
    <a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[s, datasize] = data&lt;datasize-1:0&gt;;
    <a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[s+1, datasize] = data&lt;2*datasize-1:datasize&gt;;</p>
    </div>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
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